With the continues upgrading of technology nodes and improvement of lithography resolutions in the integrated circuit manufacturing process, the size of the analyzable minimum line width of the lithography process is gradually decreasing, then the depth of focus is also rapidly reducing, therefore, lithography process windows are also becoming smaller and smaller.
However, the number of layers in the production design is increasing. Especially for the metal dielectric layers, the surface planarization of the metal dielectric layers can greatly impact the depth of focus and the stress distribution of interconnection structures, etc., which are required in the lithography process. For the integrated circuits with several layers, the surface non-planarization will seriously affect the size of the lithography process windows.
In order to ensure the validity of the lithography process windows, the surface of productions must satisfy the specific need for the planarization. In current, the chemical mechanical polishing (CMP) process is usually used to ensure the surface of the metal dielectric layers to reach the aim of planarization in the integrated circuit manufacturing process.
However, due to the variations of polishing agent selection ratios, polishing table pressures, surface patterns of products, and so on, the absolute planarization of the chip surface cannot be reached after the CMP process, replaced by the topology wrinkles, which are usually described by the dielectric dishing and the dielectric corrosion. Wherein, the dielectric dishing refers to a thickness difference between two different dielectric layers at the patterned regions, while the dielectric corrosion refers to a thickness difference between the patterned regions and the unpatterned regions.
The dielectric dishing and the dielectric corrosion are accompanied problems by the CMP process, the oversize of the dielectric dishing and the dielectric corrosion will affect the size of the lithography process windows, especially for the single exposure shot. At the same time, the resistance and the capacitance properties of the interconnected lines are also affected, thereby the delay of the interconnected lines is impacted, and further the yield and performance of chips are influenced.
In order to improve the yield of the chips and reduce production costs, the surface patterns of products would be predicted in advance after the CMP process.
The CMP simulation method of the prior art, which predicted the surface patterns of products by building a model based on the manufacturing processes, firstly collected the data from all process steps in the order of production steps to debug out the corresponding process models, and then extracted the geometry features of the surface patterns to calculate out its final prediction results. However, there are also some disadvantages listed as follows:                1) Cumbersome steps;        2) Large amount of data collected;        3) Large computation of model prediction;        4) Large period of production prediction.        
The disadvantages would lead to too long period of results output during the model prediction, so that it is adverse to shorten the production period of products.